The invention relates to technology for limiting interference associated with the communication of data by one circuit to one or more others over a serial link.
In order to reduce the pin count of an Integrated Circuit (IC), high performance serial interfaces are often used to communicate control signals and/or data between IC's. As but one of a number of possible examples, the so-called “DigRF” interface is a known, standardized serial interface. A characteristic of serial communication is the sequential transmission of one bit at a time. This can be contrasted with parallel communication, in which two or more bits are communicated simultaneously.
For a serial interface, data are formatted in a frame before being supplied for serial transmission over the interface. This is typically accomplished by buffering the data between the source of the data (e.g., a data processing block) and the serial interface block (circuit) that will actually supply the bits to the serial interface. Buffering is similarly present on the receiver side. This aspect is illustrated in FIG. 1, which is an exemplary block diagram of a circuit arrangement 100 that enables a first IC (“ICI1”) 101 to communicate frames of data over a serial interface to a second IC (“IC2”) 103.
In this example, a data processing block 105 supplies data 107 to a First-In-First-Out (FIFO) buffer 109. The data 107 is written into the FIFO buffer 109 under the control of a write clock (WCLK) signal 111.
Data 113 is read out of the FIFO buffer 109 and supplied to a serial interface transmit block 115, which controls this read operation by means of a read clock (RCLK) signal 117. A link 119 connects the output of the serial interface transmit block 115 to the input of a serial interface receive block 121 that is part of the second IC 103.
Components within the second IC 103 are present and arranged essentially in mirror image to those of the first IC 101. Accordingly, the serial interface receive block 121 writes the received data 123 to a FIFO buffer 125 under the control of a WCLK signal 127.
The received data stored in the second IC's FIFO buffer 125 is supplied by means of a connection 129 to a data processing block 131, which controls the reading of the FIFO buffer 125 by means of a RCLK signal 133.
Different mechanisms can be used to trigger the sending of a frame over the interface. The most common are:                Using a threshold fill level (watermark) of a buffer (e.g., the FIFO buffer 109 of FIG. 1). When the amount of data stored in the buffer reaches the threshold, a frame of data is read from the buffer and sent over the interface from the transmitter to the receiver.        Using a timer that generates a “tick” on a regular basis. The occurrence of each tick triggers the reading of data from the buffer and the sending of the frame over the interface from the transmitter to the receiver.        
The communication of control signals over a serial link is usually not a significant source of interference because the amount of transmitted data is typically low, with low timing coherency. The same is not true with respect to the communication of data because data processing blocks usually transfer data at a regular rate. The rate of transmission is directly linked to processing speed divided by frame size in accordance with:FFR=FDP/N where:
FFR is the frequency of transmission of a frame over the serial interface;
FDP is the frequency at which the data processing block supplies data at its output; and
N is the number of data words per frame.
A problem therefore arises in conventional technology because the regularity of serial link activity can generate Electro-Magnetic Interference (EMI) that can disturb the operation of sensitive circuitry. The source of the interference can be external to the device (i.e., the link itself) and/or internal to the device. There are several mechanisms that could lead to interference. A typical case is caused by a pattern of current consumption peaking during transmission of a frame followed by a period of no current consumption until a next frame is transmitted. This behavior creates a type of square wave signal that is applied to the power supply and leads to spurious signals being spaced apart at a rate of F.
In view of the above problems, it is desired to provide technology (e.g., methods, apparatuses, etc.) that are capable of limiting the interference that can be caused by the transmission of frames via a serial link.